module nsync
	(clock, resetn, inn, out);
input			clock, resetn;
input			inn;
output			out;

reg		[1:0]	Q;
assign			out = Q[1] & (~Q[0]);

always @(posedge clock or negedge resetn)
begin
	if (!resetn)	Q <= 0;
	else
	begin
		Q[0] <= inn;
		Q[1] <= Q[0];
	end
end

endmodule